DC-DC converter is widely used in today's electrical device. By using an inversion circuit cascaded with a rectification circuit and a filter circuit, the DC voltage is inverted to an AC voltage and the AC voltage is then rectified and filtered to the required DC voltage.
Among several inversion topologies, the half-bridge converter (HBC) has low voltage stress on semiconductors so that it is widely used for high input-voltage low-to-medium power inversion applications.
However, half-bridge topology has a pulsating input current waveform, which is a common characteristic of buck-derived converters. This pulsating input current generates high di/dt (rate of current change) noise. In addition to dv/dt noise, this di/dt noise becomes another key inducing factor of the electromagnetic interference (EMI) problem. Consequently, a large input filter must be added to meet the EMI regulation, which increases the cost and occupies space in the converter.
To reduce input current-ripple with its related di/dt noises, several ripple reduction converters have been invented recently, such as in U.S. Pat. No. 7,515,439, issued on Apr. 7, 2009 in U.S. Pat. No. 7,957,161, issued on Jun. 7, 2011, U.S. Pat. No. 8,259,469, issued on Sep. 4, 2012, and U.S. Pat. No. 8,665,616, issued on Mar. 4, 2014, all to the inventor of the present invention.
Among them, the half-bridge converter with input current ripple reduction (HBC-CRR) preserves the advantages of the HBC through the use of a current ripple reduction mechanism as shown in FIG. 2 and FIG. 3(b) of the U.S. Pat. No. 8,665,616. Therefore, smaller components of the EMI filter stage can be used instead.
However, the HBC-CRR employs symmetrical control scheme to regulate the output voltage resulting in varying the dead-time interval under different line and load operating conditions. Consequently, it operates with hard-switching resulting in higher switching losses. The operating frequency is thus limited and the reactive components, such as inductor and capacitor, are unable to reduce their size. It hinders to achieve high power density performance.
Without compromising the converter efficiency, therefore, zero-voltage switching operation should be incorporated with the HBC-CRR so that the switching frequency can be increased. However, it has not been explored yet and becomes the motivation of the present invention.
To enable a ZVS operation, two operating conditions should be met: (1) a fixed dead time between the two control driver signals, and (2) a sufficiently large energy transition between the leakage inductance (or magnetizing inductance) and the output capacitance of the MOSFET.
Among several control schemes, the required fixed dead time can be obtained by using the asymmetrical pulse-width-modulation (APWM) control or near 50% duty cycle variable frequency (VF) control schemes. Consequently, the HBC-CRR will feature the desirable zero-voltage switching operation if either one of the APWM or VF control scheme is applied.
Moreover, minimizing the conduction loss of the MOSFETs becomes another motivation of the present invention. It can be obtained by taking the advantage of lower equivalent RDS(on) (i.e. the resistance when MOSFET is turned-on) with two low-voltage rating MOSFETs connected in series. The conduction losses are thus reduced and the efficiency of the converter is improved.
In addition to having low input current-ripple performance, the present invention is directed to disclose inversion circuits and their corresponding low output current ripple rectification circuits with additional enhanced soft-switching operation performance accordingly.